Abstract
Spin-transfer torque random access memory (STT-RAM) is a potentially revolutionary universal memory technology that combines the capacity and cost benefits of DRAM, the fast read and write performance of SRAM, the non-volatility of Flash, and essentially unlimited endurance. In order to realize a small cell size, high speed and achieve a fully functional STT-RAM chip, the MgO-barrier magnetic tunnel junctions (MTJ) used as the core storage and readout element must meet a set of performance requirements on switching current density, voltage, magneto-resistance ratio (MR), resistance-area product (RA), thermal stability factor (¿) , switching current distribution, read resistance distribution and reliability. In this paper, we report the progress of our work on device design, material improvement, wafer processing, integration with CMOS, and testing for a demonstration STT-RAM test chip, and projections based on modeling of the future characteristics of STT-RAM.
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