Process variation aware data management for STT-RAM cache design

Abstract

The spin-transfer torque random access memory (STT-RAM) has gained increasing attentions for its high density, fast read access, zero standby power, and good scalability. The recently proposed retention-relax design further improves STT-RAM write access performance and makes it even more promising as an on-chip memory technology. Nevertheless, the process variations could affect the writability of STT-RAM cells. The situation for retention-relax design is even more severe. In this paper, we comprehensively study the impact of process variations, including those from both CMOS and magnetic technologies, on key STT-RAM design parameters. Furthermore, we propose process variation aware nonuniform cache access (PVA-NUCA) technique for large STT-RAM cache design. Besides the varying interconnect latencies determined by memory locations, PVA-NUCA compensates write time variations of STT-RAM cells resulted by process variations. Two algorithms, namely, conservative promotion and aggressive prediction, have been introduced and evaluated. A conflict-reduction mechanism is utilized to degrade the data access miss rate caused by conflicts of access-intensive data blocks. Compared to the traditional STT-RAM dynamic nonuniform cache access (DNUCA), our proposed dynamic PVA-NUCA can improve 25.29% of IPC performance and reduce 26.4% of STT-RAM cache energy consumption, with