Abstract
Design-for-testability (DFT) is widely used in current integrated circuit design to enhance the controllability and observability of signals. The technologies insert extra logics into an original design, running in test mode without any functional influence. How to make all the test logics work harmoniously and obtain high fault coverage with low area and performance overhead are the two main issues of DFT. Based on the design of a general-purposed CPU chip, this paper introduces some advanced topics to conquer the problems, including technologies of memory built-in-self-test (BIST), internal scan design, logic BIST, IEEE Std. 1149.1 (JTAG)-compatible boundary scan design and the correlations among them. These technologies offer a convenient and reliable DFT scheme for digital circuit designs, especially for large-scale ones, like a general-purpose CPU chip.
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