Abstract
Contact resistance is becoming an important limiting factor for achieving high MOSFET drive current and speed in future technology nodes. In this paper, we review the technology solutions for reducing the contact resistance between a metal silicide contact and the source/drain region. Several new approaches for decreasing the electron and hole barrier heights between the source/drain region and the silicide layer in n-FET and p-FET, respectively, will be examined. Integration of these approaches in advanced device architectures will be discussed.
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