Advanced processing techniques for through-wafer interconnects

Abstract

The fabrication of interconnects used in future microelectronic devices and for three-dimensional (3D) integration of these components will require advanced integrated circuit (IC) processing techniques. One attractive approach to providing increased connectivity is to use through-wafer interconnects. The primary challenge to implementing 3D stacking is the formation of these high aspect ratio interconnects with a sufficiently small diameter and, consequently, with sufficiently high density. Processing techniques to fabricate through-wafer interconnects in silicon for applications that require multichip stacking or contacts on both sides of the wafer will be described. The techniques used for fabrication of the vertical interconnects are compatible with complementary metal–oxide–semiconductor technology and executed within the thermal budget of a completed IC. The processing techniques to be described include: deep silicon etching (DRIE) to form small diameter vias, insulator lining, adhesion/barrier layer deposition, seed layer deposition, copper electroplating, and chemical mechanical planarization of copper. Through-wafer copper interconnects have been formed with via diameters of 50–100 μm on 4 and 6 in. silicon wafers containing no active devices and at temperatures no greater than 200 °C.