Advanced MTJ and SOT Technology for AI and Automobile applications INVITED

Abstract

Introduction: Double CoFeB/MgO interface perpendicular MTJ has become the de facto standard technology of current STT-MRAM. However, there are still issues for high density memory application and high reliable application including Automobile applications. Furthermore, achievement of high speed and high endurance features, in the other words, high speed SRAM replacement is still challenging for STT-MRAM, because of its tradeoff relationship among the retention, endurance, and operational speed. Recently, Spin Orbit Torque (SOT) devices have been intensively researched and developed because SOT devices have the potential to achieve high speed and high endurance. To realize the practical use of SOT-MRAM for LSI applications, these issues must be addressed.This invited paper reviews our recent progresses in STT-MTAM, SOT-MRAM and Nonvolatile AI processors with CMOS/MTJ hybrid technology. The STT-MRAM and SOT-MRAM as NV working memory and AI processors as these applications are particularly suitable for future IoT / AI systems that require ultra-low-power and high-performance computing at the same time.128Mb STT-MRAM and Quad interface MTJ technology: We developed novel damage control integration process technologies including new low-damage MgO deposition process, low-damage RIE process, and low temperature SiN-cap process. By applying the developed damage control integration process technologies to double interface p-MTJ fabrication, TMR ratio, thermal stability factor, and switching efficiency of Double p-MTJ were successfully improved. Moreover, it was shown that despite the significant increase in thermal stability factor, the endurance of the fabricated Double p MTJs was over 1010. Finally, with our double-interface p-MTJ technology and novel damage control integration process technologies, fabricated 128Mb STT-MRAMs successfully achieved 14ns/7ns write speed at Vdd of 1.2V/1.8V, respectively.Next, for further scaling of STT-MRAM, we proposed novel Quad-interface p-MTJ technology which brings forth an increase of thermal stability factor compared with conventional Double-interface p-MTJ technology. We successfully fabricated the quad-interface MTJ using 300mm process based on the damage control integration process. The fabricated Quad p-MTJs achieved an enhancement of switching efficiency in addition to an approximately two times larger thermal stability factor without degradation of TMR ratio. The developed Quad p-MTJ technology will become an essential technology for the scaling of the STT-MRAM beyond 20nm without changing material and process sets from mass-production STT-MRAM. Moreover, the high reliable Quad p-MTJ technology with enough thermal stability factor is suitable for Automobile applications that require high temperature operation such as 150○C.Field-free canted SOT-Device with 350ps write speed and its SOT-MRAM: To realize practical use of SOT-MRAM for LSI applications, we demonstrated 55 nm-CMOS/SOT-device hybrid MRAM cell with magnetic field free writing for the first time. For field free writing, we developed canted SOT device under 300 mm BEOL process with 400°C thermal tolerance. In addition, we developed its advanced process as follows; PVD process of SOT channel layer for high spin Hall angle under 400°C thermal tolerance, low damage RIE technology for high TMR/thermal stability factor, and ultra-smooth surface metal via process under SOT device to reduce contact resistance. By using the developed technologies, our canted SOT devices achieved fast write speed of 0.35 ns without magnetic field, an enough thermal stability factor of 70 for non-volatile memory (over 10 years retention), and a high TMR ratio of 167%, simultaneously. Moreover, we fabricated a field free canted SOT-MRAM cell with 55 nm CMOS technology and demonstrated its write/read performance. These technologies will open to high speed write non-volatile memory such as 1 level cache application of many kinds of application processors.CMOS/MTJ hybrid AI Processor for low power application: Focusing on the indispensable nearest neighbor search (NNS) function of the brain, we developed a nonvolatile object recognition processor with NSS full-adaptive to any data format, employing nonvolatile memories base on our p-MTJ. The developed object recognition processor was fabricated under 90nm-CMOS/70nm-MTJ hybrid process on 300mm-wafer. The 4-Transistors & 2-MTJs type memory cells were adopted to completely eliminate standby power. Moreover, we successfully developed a self-directed power-gating technique leveraging the non-volatility, high access speed and unlimited endurance features of the p-MTJs. This developed self directed power-gating technique was employed to shut down idle circuit blocks during not only the standby periods but also the full operation periods. The measured peak operation power consumption of the prototype chip was only 130μW and can be further optimized corresponding to the format of reference data. Compared to the latest conventional researches, the significant improvements of both power performance (about 2-3 order reduction) and circuit density (about 2 order improvement) were achieved. **