Advanced laminate carrier module warpage considerations for 32nm pb-free, FC PBGA package design and assembly

Abstract

The trend in large body, high performance integrated circuit packaging for the 32 nm semiconductor node and beyond is towards low dielectric loss to enable high bandwidth / low loss channels, and low thermal expansion to protect fragile, ultra-low dielectric constant (k) chip dielectric materials from differential expansion stress. A low coefficient of thermal expansion (CTE), low dielectric loss laminate composite was developed using industry standard Sequential Build Up (SBU) fabrication techniques and novel laminate materials. This laminate technology was used in assembly of a Flip Chip Plastic Ball Grid Array (FC PBGA) module including a silicon test structure developed for 32 nm Custom Logic development. The same silicon test structure and laminate design were also used to fabricate modules using conventional high volume laminate materials. Various laminate physical parameters including composite CTE were determined. The warpage shape of each laminate was initially characterized at room temperature, and over the temperature range from 25°C to 240°C. Warpage of critical package features was measured and tracked throughout the various steps of the lead free flip chip module assembly process for multiple laminate cross sections, core and buildup materials. A quantity of assemblies of each type was built and measured, data is reported. Advantages and disadvantages of each laminate module type and implications for robust package assembly as evidenced by these results are discussed.