Advanced Assembly Process Development For Ultra Fine Pitch Wafer Level Packaging

Abstract

The 2003 ITRS roadmap identifies the need for peripheral I/O flip chip direct chip attach at 30/spl mu/m pitch in 2007 and 20/spl mu/m pitch in 2009. Area array flip chip packaging is expected to reach 90-100/spl mu/m pitch in 2010. The drivers for such a reduction in pitch are two-fold: 1) higher I/O density on the IC due to the higher transistor density, and lower standoff height of 5-10/spl mu/m, 2) interconnects to reduce electrical parasitics to enable higher signal speed and bandwidth. Recent accomplishments include development of a high reliability flip chip assembly process for no flow underfills enabling virtually void free assembly based on a new hybrid assembly process. A lead free solder flip chip process using Sn-Ag-Cu alloy has been developed and qualified to >1000 cycles to first failure. Predictive reliability models for flip chip on board and in package have also been developed based on a correction function approach allowing designers to account for factors such as surface metallization, void formation, etc, difficult to account for in FEM modeling. This paper describes the process development of 100/spl mu/m pitch die assembly with several interconnect schemes with different materials and processes. Within these interconnect schemes proposed, one of the interconnect scheme has the optimum properties regarding thermomechanical reliability, electrical performance and low cost. Since it was found that the requirements of electrical performance often conflict with those thermomechanical reliability, the optimum build is derived with the trade offs between required properties mentioned and tested to meet the manufacturing quality. Two distinct assembly processes will be applied to deriving high reliability flip chip assembly. The first process that is applied is by using the traditional solder. For such fine pitch, 100/spl mu/m pitch, it is rather difficult to clean off the flux in the post reflow process. For capillary flow flip chip process, high reliability is achieved by having low flux residue after the reflow. The less the flux residue after the reflow, less underfill voiding results. Currently, various commercial fluxes and known good processes have been attempted for 100/spl mu/m pitch assembly. However, it is difficult to achieve the good yield without using excessive flux. By that means, lot of the flux residues can be found after the reflow enabling early failure in reliability screening. Various commercial fluxes are tested and for the best performing material, all reflow parameters are optimized to give good interconnect. One other approach of assembly that is applied is gold to gold interconnect using compression bonding method. This process is extremely attractive, since it requires no reflow process. Commercial non- conductive paste and anisotropic conductive films are tested for the search of optimal build condition. These processes are revised again to undergo further research on finer pitch wafers. Major benefits of such an accomplishment can provide a commercialized process of high I/O with reliable interconnect. The flip chip process is used to give the best electrical and mechanical performance of interconnect.