Advanced 3DIC Die Stacking for Memory and Mobile Applications

Abstract

This paper presents the developmental progress and status for the assembly of multi-die, stacked 3D IC packages. Die stacking with TSV technology represents a critical path for future memory and mobile devices. The assembly of these complex stacks involves the extension of existing methods combined with the development of advanced backside wafer finishing. Assembly options including memory to logic, 2+memory to logic, and 2+memory configurations will be reviewed, including perspective assembly methodologies. Alternative assembly methodologies including die to die, die to substrate and die to wafer will be reviewed.