Adiabatic logic based circuit optimization for ultra low power applications

Abstract

In this paper authors have presented a design and experimentation evaluation of circuit optimization inspired by adiabatic logic processing. The reported work inherent the power benefits associated with adiabatic charge transfer process. Simultaneously it also addresses an important issue of optimizing the high transistor count as required in traditional adiabatic logic families. Therefore the proposed hybrid adiabatic logic family not-only optimize the circuit area along with power but also it removes the requirement of dual polarity inputs for circuit actuation. Different circuits are optimized and implemented using the reported work in 180nm technology with trapezoidal power clock. The results obtained are compared with circuits available in previous works. The functional verification and result measurements proved the advantages associated with the proposed circuit optimization for energy efficient implementation for very-large scale integrated (VLSI) circuits