Abstract

This paper presents some additional high input low output impedance analog networks realized using a recently introduced single Dual-X Current Conveyor with buffered output. The new circuits encompass several all-pass sections of first- and second-order. The voltage-mode proposals benefit from high input impedance and low output impedance. Nonideality and sensitivity analysis is also performed. The circuit performances are depicted through PSPICE simulations, which show good agreement with theory.

Highlights

  • In the recent past, realization of configurable analog networks has assumed special significance for modern analogue signal processing applications

  • The feature is quite suited while designing analog blocks with easy configurability, so as to be employed in field programmable analog arrays (FPAAs)

  • The most recent analog circuit topology benefits from these features by being suited for a number of first-order electronic functions and offering high input impedance and low output impedance [5]

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Summary

Introduction

Realization of configurable analog networks has assumed special significance for modern analogue signal processing applications. The feature is quite suited while designing analog blocks with easy configurability, so as to be employed in field programmable analog arrays (FPAAs). Whereas configurability gives rise to the possibility of several electronic functions from a single topology, cascadability results in practical utility of analog blocks for designing more complex networks without additional coupling elements in form of buffers [4,5,6]. The most recent analog circuit topology benefits from these features by being suited for a number of first-order electronic functions and offering high input impedance and low output impedance [5]. It may be noted that floating inductor simulators using current conveyors have been researched well in the literature [14,15,16,17]. Extensive simulations are performed to validate the proposed theory, which justify the proposed theory and provide advancement to the existing knowledge

Additional First-Order All-Pass Filters
Second-Order Filters
C3L sim
Nonideal Analysis
Parasitic Considerations
Simulation Results
80 MHz Frequency
Conclusion
Full Text
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