Adaptive security monitoring for next-generation routers

To support the flexibility and the different protocol operations and applications provided by today's internet, modern routers rely on high-performance reliable general-purpose multi-core packet processing systems. Such processing systems are programmable and have replaced the traditional fixed-logic hardware in the data path of such routers. This programmability introduces a lot of vulnerabilities and faults which make such systems susceptible to attacks and failures. Particularly, it is a difficult task to detect whether a processing core behaves correctly or it has a failure resulting from errors or attacks. In this paper, we address this problem by proposing a novel approach to verify the correct operation of the network processor. We propose a secure, fault tolerant and reliable monitoring subsystem which functions in parallel with the processing core of the router and aids in the detection of attacks. We show that our system has the ability to detect the failure and restore securely the router's operation to a different, but functionally equivalent state.

In today's modern networks, routers rely on high-performance multi-core packet processing systems to implement a variety of applications and operations required to forward traffic. This leads to an increase in the complexity of such systems and hence the number of processing cores. Managing such processing cores and ensuring their correct operation become a difficult task. In this paper, we address this problem by proposing another novel approach to verify the correct operation of network processor and detect any attack/failure. This approach monitors the power consumption of such cores at the OS level during run-time and correlates it statistically with predetermined benchmark information. We show that based on this correlation, any failure/attack can be detected.

High-performance multi-core packet processing systems are the building blocks of every modern router in today's networks. Such multi-core processors are required to implement complex protocols and applications on routers. However, managing such systems and ensuring their correct operation at runtime becomes a difficult problem to solve. It is particularly hard to detect whether a processing core behaves correctly or it has failed due to a system error or an attack. In this paper, we address this problem by proposing a novel approach to verify the correct operation of the network processor. This approach treats the network processor as a black box and monitors its power consumption. We show that by comparing the power consumption with benchmark information, any failure can be detected easily and its origin can be determined.

Modern routers use high-performance multi-core packet processing systems to implement protocol operations and to forward traffic. As the diversity of protocols and the number of processor cores increases, it becomes increasingly difficult to manage these systems and ensure their correct operation at runtime. In particular, it is challenging to identify situations in which a part of processor cores behave incorrectly, either due to failure or due to malicious attacks. To address this problem, we present a novel approach to verifying correct operation of a packet processor by analyzing packet latency and throughput. This approach can treat the network processor as a “black box” and does not need to observe internal functionality. We show that processing time statistics are affected by system misbehavior and present an analytic model to quantify these effects. Our results show that the presented technique is an effective approach to provide an extra level of protection to packet processor systems.

This paper proposes multiple clustered core processors as a solution that attains both low power consumption and easy programming facility. Considering the current trend of increasing power consumption and temperature, a lot of CPU venders have shipped or announced to ship multiple core processors. Especially, recent studies on heterogeneous multiple core processors show that they are more efficient in energy utilization than homogeneous ones. However, they request programmers to consider complex task scheduling since the size of every task always has to match the performance of core where it is allocated. Multiple clustered core processors relieve them from such a tedious job. Simulation results show that a multiple clustered core processor consumes slightly more power than a heterogeneous multiple core processor. However, in a case, the heterogeneous multiple core processor cannot solve a severe task scheduling problem, while the multiple clustered core processor can.

Applications executing on multicore processors can now easily offload computations to many core processors, such as Intel Xeon Phi coprocessors. However, it requires high levels of expertise and effort to tune such offloaded applications to realize high-performance execution. Previous efforts have focused on optimizing the execution of offloaded computations on many core processors. However, we observe that the data transfer overhead between multicore and many core processors, and the limited device memories of many core processors often constrain the performance gains that are possible by offloading computations. In this paper, we present three source-to-source compiler optimizations that can significantly improve the performance of applications that offload computations to many core processors. The first optimization automatically transforms offloaded codes to enable data streaming, which overlaps data transfer between multicore and many core processors with computations on these processors to hide data transfer overhead. This optimization is also designed to minimize the memory usage on many core processors, while achieving the optimal performance. The second compiler optimization re-orders computations to regularize irregular memory accesses. It enables data streaming and factorization on many core processors, even when the memory access patterns in the original source codes are irregular. Finally, our new shared memory mechanism provides efficient support for transferring large pointer-based data structures between hosts and many core processors. Our evaluation shows that the proposed compiler optimizations benefit 9 out of 12 benchmarks. Compared with simply offloading the original parallel implementations of these benchmarks, we can achieve 1.16x-52.21x speedups.

With the evolution of multi-core Systems, the computing performance has been improved and these processors with more than one processing cores has found there application in the fields where high performance and complex computation is required like supercomputing, remote monitoring systems, data mining, data communication and processing systems etc. Multi-core processors can be utilized to improve the performance of embedded and real time systems. As the scheduling capability of the Real Time Operating System (RTOS) determines its efficiency and performance when dealing with real-time critical tasks, use of more than one processing units speeds up the task processing. This paper presents an algorithm called ParaRMS, which is a Rate Monotonic Scheduling (RMS) algorithm in parallel on multi-core architecture and has been scheduled on a multi-core system. This improves the scalability and responsiveness of the Rate monotonic scheduling algorithm which will also help scheduling the dynamic tasks effectively and offers good CPU utilization for given task set. In support of this work, analysis of ParaRMS has been carried out on Intel VTune Amplifier XE 2013 with positive results.

In information systems, applications are required to be realized in the digital ecosystems, high performance systems, and scalable systems. In these applications, a client first selects a server in a cluster of servers and issues a request to the server. The request is performed as a process in the server. In this paper, we consider a computation process which mainly consumes the central processing unit (CPU) resources. Cooling devices, such as fans, consume the electric power in addition to the CPU of a server. The rotation speed of a fan is revved up in servers in order to decrease the temperature of a server. Thus, the total power consumption of a server depends on not only computational devices such as a CPU, but also cooling devices. We discuss an extended simple power consumption (ESPC) model of a server with a multicore CPU and cooling devices to perform computation type processes. It is critical to discuss how to select a server for each request issued by a client in order to not only achieve performance objectives, but also reduce the total power consumption of a system based on the ESPC model. An improved power consumption laxity-based (IPCLB) algorithm for selecting a server is proposed in this paper, where the minimum power to be consumed is used to perform the process. We evaluate the ESPC model and IPCLB algorithm in terms of power consumption and elapse time.

Chapter 3 - Multi-core Processors and Embedded

A high-performance image processing system (HIPS) has been developed to provide two- dimensional image acquisition for a variety of opti- cal applications. The system is built around two high-performance visible-light charged coupled device(CCD) arrays: a 32-port, 1024 x 1024 pixel array anda 16-port, 512 x 512 pixel array. The arrays and as- sociated circuitry were designed to operate at high frame rates, with an optical power dynamic range ofover 30 dB. The 512 x 512 array is designed to operateat over 800 frames per second; the larger device, atover 300 frames per second. The system has two main units: a stand-alone high-performance camera array module (HPCAM)and a VME-based image capture and display system(ICADS). HPCAM contains a CCD array and associ-ated drive and control electronics. ICADS consists ofan analog multiplexer, digitizer, digital frame buffer-integrator, main central processing unit (CPU) board with user and Ethernet interfaces, graphics driver, and high-resolution monitor.The CCD arrays used in this work are designed foruse in optical processing systems, such as radar ambi-guity, wide-band signal detection, and synthetic aper-ture radar (SAR) image formation processors. Thissystem provides a method for capturing and display-ing CCD array output data, giving the researcher amethod to analyze and develop CCD array and opti-cal processing systems.

Chip multi-processors (CMPs), commonly referred to as multi-core processors, are being widely adopted for deployment as part of the grid infrastructure. In CMPs, multiple cores can independently execute different threads. This change in computer architecture requires corresponding design modifications in programming paradigms, including grid middleware tools, to harness the opportunities presented by multi- core processors. Simple and naive implementations of grid middleware on multi-core systems can severely impact performance. The goal of developing an optimized multi-threaded grid middleware for emerging multi-core processors will be realized only if researchers and developers have access to an in-depth analysis of the impact of several low level microarchitectural parameters on performance. None of the current grid simulators and emulators provides feedback at the micro-architectural level. We have designed an emulation framework, Multi-core Grid (McGrid), to analyze and provide insightful feedback on the performance limitations, bottlenecks, and optimization opportunities for grid middleware on multi-core systems.

Central processing unit (CPU) for any computer generally operates at constant power supply voltage. Normally in product specification, this power supply voltage has tolerance margin close to ±5%. It is shown in the previous works that for every millivolt drop in power supply voltage, the operation frequency of a chip reduces by about 2 MHz. This voltage drop occurs when CPU starts drawing current from the power supply. It is desirable to maintain the supply voltage within the specification of allowed voltage fluctuations so that the CPU can run at the target operating frequency, for a given package inductance and die decoupling capacitance. In this paper, power supply noise reduction method for multicore CPU in a given silicon chip has been considered. The concept of variable frequency has been applied on every core to minimize the noise by changing the current ramp of a multicore system. This reduces the dI/dt, and therefore for fixed package inductance and die decoupling capacitance, the power supply noise reduces. In this paper, four-core CPU has been taken and also shown the reduction of noise by changing the current ramp using variable clock frequency on each core and also by staggering the time when each core will start clocking.

Visualizing 3D/4D environmental data using many-core graphics processing units (GPUs) and multi-core central processing units (CPUs)

Single-instruction multiple-thread (SIMT) machine emerges as a primary computing device in high-perfor-mance computing, since the SIMT execution paradigm can exploit data-level parallelism effectively. This article explores the SIMT execution potential on homogeneous multi-core processors, which generally run in multiple-instruction multiple-data (MIMD) mode when utilizing the multi-core resources. We address three architecture issues in enabling SIMT execution model on multi-core processor, including multithreading execution model, kernel thread context placement, and thread divergence. For the SIMT execution model, we propose a fine-grained multithreading mechanism on an ARM-based multi-core system. Each of the processor cores stores the kernel thread contexts in its L1 data cache for per-cycle thread-switching requirement. For divergence-intensive kernels, an Inner Conditional Statement First (ICS-First) mechanism helps early re-convergence to occur and significantly improves the performance. The experiment results show that effectiveness in data-parallel processing reduces on average 36% dynamic instructions, and boosts the SIMT executions to achieve on average 1.52× and up to 5× speedups over the MIMD counterpart for OpenCL benchmarks for single issue in-order processor cores. By using the explicit vectorization optimization on the kernels, the SIMT model gains further benefits from the SIMD extension and achieves 1.71× speedup over the MIMD approach. The SIMT model using in-order superscalar processor cores outperforms the MIMD model that uses superscalar out-of-order processor cores by 40%. The results show that, to exploit data-level parallelism, enabling the SIMT model on homogeneous multi-core processors is important.

Signal integrity and associated optimization techniques in power delivery network for multi-core processors, whether powered by a single converter or several power converters, are discussed. The high integration of the multi-core processors on a single die makes chipset's sensitivity to crosstalk noise more likely. Several power converters in a multi-core processor system could improve energy efficiency and dynamic performance among others. However, this paper focuses on how several power converters can be used to achieve over 60dB of crosstalk noise isolation. Crosstalk noise can be reduced by dedicating a power converter for each processor core (or more) and placing the power converters between the processors cores.