Adaptive Patterning of Optical and Electrical Fan-Out for Photonic Chip Packaging

Abstract

Packaging and assembly challenges for photonic chips still need to be addressed in order to enable rapid deployment in mass-market production. Integration and assembly solutions that not only enable ease of packaging but also allow a dense co-integration of the electronic and photonic ICs are essential. In that context, we demonstrate an adaptive patterning of both optical and electrical fan-out for face-up electronic-photonic integration. For the optical fan-out, we developed an approach based on adiabatic optical coupling between single-mode polymer waveguides and silicon waveguides on a silicon photonic chip. The polymer waveguides were directly patterned on the silicon photonic chip by direct-write lithography (DWL). The electrical interconnects between a photonic chip and electronic IC are realized by employing high-speed silver interconnects using aerosol-jet printing (AJP), as a promising alternative for the traditional bond-wires. Furthermore, a direct comparison between the AJP interconnects and the conventional bondwires is established. Finally, an NRZ optical transmitter has been successfully demonstrated based on the AJP interconnection and clear open eye diagrams were obtained at 56 Gb/s.