Adaptive Miller capacitor multiplier for compact on-chip PLL filter

Abstract

An adaptive Miller capacitor multiplier is proposed to reduce on-chip phase-locked loop (PLL) capacitor area and improve lock speed. Fabricated in 0.5 µm standard CMOS, an effective capacitance of 576 pF is achieved with a polycapacitor of only 192 pF (62% die area saving) and 0.43 mA current consumption. The lock time is reduced by 36% due to the adaptive loop bandwidth control during PLL settling.