A low jitter phase-lock loop based on a new adaptive bandwidth controller

Abstract

This paper presents the analog adaptive phase-locked loop (PLL) architecture with a new adaptive bandwidth controller to reduce locking time and minimize jitter in PLL output for wireless communication. It adaptively controls the loop bandwidth according to the locking status. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status. It is simulated by HSPICE and achieves the primary reference sidebands at the output of the VCO at approximately -80dBc