Adaptive Low Shift Power Test Pattern Generator for Logic BIST

Abstract

Increasing the correlation among adjacent test stimulus bits can significantly reduce shift power consumption. However, it often causes test coverage loss when applying it to reduce the shift power consumption in logic BIST. In this paper, a new adaptive low shift power random test pattern generator (ALP-RTPG) is presented to improve the tradeoff between test coverage loss and shift power reduction in logic BIST. This is achieved by applying the information derived from test responses to dynamically adjust the correlation among adjacent test stimulus bits. When comparing with an existing method, called LT-RTPG, experimental results for industrial designs show that the proposed method can significantly reduce the test coverage loss while still achieving dramatic shift power reduction.