Adaptive error correction in Orthogonal Latin Square Codes for low-power, resilient on-chip interconnection network

Abstract

A reliable, energy-efficient on-chip interconnection network can be designed by incorporating error-correcting code (ECC). Orthogonal Latin Square Code (OLSC) can protect the interconnection against transient errors, supporting multi-bit error correction capability. In this paper, we propose an adaptive ECC which provides opportunity and flexibility of adaptively to change the error correction capability according to interconnection’s reliability level, reducing the power consumption of the interconnection network.