Adaptive Blind Timing Mismatch Calibration with Low Power Consumption in M-Channel Time-Interleaved ADC

Abstract

This paper proposes an adaptive blind calibration scheme to minimize timing mismatch in M-channel time-interleaved analog-to-digital converter (TIADC). By using a derivative filter, the timing mismatch can be calibrated with the coefficients estimated by calculating the average value of the relative timing errors for all sub-ADCs. The coefficients can be estimated by utilizing the filtered-X least-mean square algorithm. The main advantages of the proposed method are that the difficulty of the implementation and the power consumption can be reduced dramatically. Simulation results show the effectiveness of the proposed calibration technique. The design is synthesized on the TSMC-55 nm technology, and the estimated power consumption of digital part is about 4.27 mW with 1.2 V supply voltage. The measurement results of the FPGA validate system show that the proposed calibration can improve the SNR of a four-channel 400 MHz 14-b real TIADC system from 39.82 to 65.13 dB.