Active Processor Hardware Stack

Abstract

The characteristic features of the reduced instruction set computer (RISC) architecture are used to develop high-performance microprocessors and microcontrollers. Complex operations, which include subroutine calls and interrupt service, are difficult to implement in hardware for the same time interval with all the other commands. Such operations, when executed, involve recording the value of the transition address in the register of the processor’s software counter while saving the return address from the subroutine. A specific design of the processor hardware stack is proposed in the work, which allows performing complex machine operations in one clock cycle. It is established that the required technical result can be achieved by introducing in the design of the processor N identical software counters, which are actually analogues of the stack registers. It is shown that a stack pointer (SP) with the logic of the register selection connected to a block of program counters (PCs) activates the next PC when a subroutine is called or an interrupt is serviced, while the previous counter stores the return address from the subroutine. This excludes the procedures of saving the return address from the PC in the registers of the stack or the RAM cells and restoring its state from the stack. This allows us to make a subroutine call or jump along the interrupt vector and return to the call point in one clock cycle of the master oscillator. As a result of this, it becomes possible to increase the processor’s speed during such operations by 30–50% and improve overall performance without increasing the clock frequency.