Active Pixel Sensor CMOS Operating Multi - Sampled in Time Domain

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CMOS image systems have receiving great attention from industry and academy due to the growing demand for compact and low power image systems. Compared to charge-couple device CCD, CMOS image sensors presents as advantage higher integration capability. In general, CCD achieve better performance due to its particular fabrication process, however, they require high operation voltage and cannot be easy integrated with CMOS circuits that compound cameras. In last decades, the CMOS imager sensor technology has been improving and they are being used in several applications as multimedia and biomedicine (Fossum, 1997, Hosticka, 2003, Sandage, 1995). Dynamic range is one of the most important merit figure of image sensors. It is defined as the ratio between the maximum and minimum signal acquired. External scenes present dynamic range higher than 100dB but conventional CMOS image sensors and CCDs shows dynamic range about 60dB. Therefore, they are not able to capture properly external images. However, several researchers proposed different CMOS image sensors architectures with high dynamic range (>80 dB) (Stoppa, 2002, Trepanier, 2002, Yadid-Pecht, 2003, Yang, 2002, Yasuda, 2003, Saffih, 2007). An attractive high dynamic range architecture approach is the digital pixel sensor (DPS) (Kleinfielder, 2001). This architecture is composed by a ramp digital converter and an 8 bit memory integrated per pixel. The main advantage of this approach is the high frame rate operation however, it presents as disadvantage low fill factor. Different architectures based on DPS were proposed (Doge, 2002, Kitchen, 2004, Qi, 2004). Time-domain DPS were proposed in (Bermak, 2006) and (Chen, 2006). They are characterized by the measurement of fall time of photodiode s voltage. In general, time-domain DPS architectures integrate a comparator and a 8 bit counter in each pixel. The main disadvantage of this approach is the low fill-factor due to the great number of transistors integrated per pixel. A time-domain imager with only 10 transistors per pixel was proposed in (Lai, 2006). A pipeline operation is proposed in order to achieve high dynamic range. However this approach requires the use of two ramp, one at beginning and other at the end of the integration time reducing the sensitivity at middle range of illumination. A sampled time-domain CMOS imager was proposed in (Campos, 2008). This pixel architecture is composed by a clocked comparator and a dynamic D flip-flop integrated per pixel. The number of transistor integrated per pixel is still significantly and the fill-factor is low. However the sampling in time-domain concept proposed suggest that the comparison