Accurate modeling of direct tunneling hole current in p-metal–oxide–semiconductor devices

Abstract

We critically examine a number of important issues related to modeling hole direct tunneling in p-metal–oxide–semiconductor devices with p+-polycrystalline silicon gate. By comparing our simulated direct tunneling hole current with experimental data, several observations are made. It is found that inelastic trap scattering of holes in the gate-oxide region increases the hole tunneling current significantly at lower gate voltages in devices with gate-oxide thickness greater than 2 nm. Appropriate spatial and gate bias dependence of the scattering rate needs to be considered for accurately predicting experimental current over the entire gate voltage range. Effective mass of holes in gate-oxide region is not a constant, rather, it increases with increasing gate bias voltage and we propose a relationship between the two. Bulk values for hole effective masses in silicon may be used to accurately model the hole tunneling current even in the presence of hole quantization. The contribution of split-off holes to direct tunneling current is not negligible in strong inversion.