Abstract
A new method for the analysis of parallel transmission lines in multilayered dielectric media is presented. The method is based on adaptive mixed finite element techniques with improved error estimators. The analysis can be used to extract accurately the interconnect capacitances for circuit and timing simulators in the design and verification phases of high speed digital integrated circuits, and for fine tuning of the technological process for improved performance. As way of example the paper presents the cases of multiconductor and coplanar transmission lines, in typical GaAs IC designs.
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