Accurate evaluation of interface trap density at InAs MOS interfaces by using C–V curves at low temperatures

Abstract

A method to evaluate the interface trap density (D it) accurately by using high-frequency C–V curves at InAs MOS interfaces is experimentally examined, where quick responses of the interface traps at room temperature make D it evaluation based on the high-frequency C–V (Terman) method difficult. Therefore, low-temperature measurements of the C–V curves were performed to suppress the response of the interface traps. We studied the impact of the accuracy of the oxide capacitance C OX, distribution function, and C–V hysteresis owing to slow traps on the D it values evaluated by the Terman method. It was found that the accuracy of C OX and the choice of distribution function had a slight effect on the accuracy of the D it evaluation. It was also revealed that a measurement temperature lower than 40 K and limited gate voltage ranges in the C–V scan were indispensable for the accurate evaluation of D it.