Abstract
As oxide thicknesses begin to scale below 1.5 nm, gate tunneling currents are expected to become significant as compared to the drain current. In this paper, the impacts of parasitic gate currents on analog designs are explored. Specifically, current mirror topologies are considered because of their sensitivity to gate tunneling current and their ubiquitous use. A new current mirror topology, which relies on partially-depleted (PD) SOI devices, is developed to reduce the effects of gate tunneling current. These circuits were verified through simulation in a 90 nm IBM SOI technology.
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