Accurate Boundary Condition for Short-Channel Effect Compact Modeling in MOS Devices

Abstract

In this paper, the boundary conditions at the edges of the junctions are discussed, and their consequences on the compact modeling of short-channel effects (SCEs) in MOSFETs are investigated. It is first shown that the previous voltage-doping transform (VDT) potential model does not agree with the simulation results when the impact of lightly doped drain regions or thin spacers are considered. A solution is then proposed to correct the channel potential model using more accurate boundary conditions at the edges of the channel, which consist in calculating an accurate effective built-in potential value V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bi</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sup> at the source and at the drain. The impact of these improved boundary conditions on compact models of SCEs is investigated. It is shown that the previous VDT models of drain-induced barrier lowering and subthreshold swing for all types of fully depleted devices can be very simply corrected to finely agree with the simulations without fitting parameters. These models finally allow to investigate the impact of the doping concentration of the junctions on the device performance.