Abstract
Severe process variations in advanced technology require more devices under test (DUTs) to be characterized in the wafer acceptance test (WAT) to more reliably qualify the fabricated wafers. However, conventional WAT takes a long test time to acquire sufficient characterization data. This article proposes an on-wafer test circuity to fast and accurately characterize DUT arrays during a single probing. It integrates the proposed compact DUT cells, an IR drop compensator, and a wide-input-range (WIR) current digitizer. The proposed IR drop compensator collaborates with the DUT cells to address the IR drop issue and thus improve the test accuracy of the parameter tests. The proposed multi-mode 12-bit WIR current digitizer achieves a 140-dB input range for digitizing the DUTs’ output currents in various WAT test items. It eliminates the need of high-end ATE and saves the test cost. A prototype IC including 2048 DUTs has been designed and fabricated in 90-nm CMOS. Its active area is only <inline-formula> <tex-math notation="LaTeX">$60~\mu \text{m}$ </tex-math></inline-formula> by <inline-formula> <tex-math notation="LaTeX">$1900~\mu \text{m}$ </tex-math></inline-formula> which can be placed in a scribe line as conventional WAT structure is. Experimental results demonstrate the proposed test circuitry can render spatial variation results and other device parameters of the DUT arrays in addition to typical WAT items.
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More From: IEEE Transactions on Circuits and Systems I: Regular Papers
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