Novel in-line WAT processing of 55 nm CIS product and effect of process waiting time on void growth at interface of SiCN with copper capping layer

Abstract

The WAT (wafer acceptance test) is the last examination that is performed before a wafer or a chip fab out to ensure the quality and stability of chip performance. In 55 nm CIS (CMOS Image Sensor) technology, a highly smooth wafer surface is critical for the BSI (backside illumination) process. The traditional WAT process cannot be used; rather the in-line WAT must be performed during the process for forming copper interconnect. However, increasing the processing time increases the period of exposure of the copper interconnect to air, which is called the Q-time, affecting the reliability of copper interconnect. Nitrogen-doped silicon carbide (also called NDC or SiCN) has been used to fabricate copper diffusion barrier films. PECVD SiCN dielectric has a promisingly low dielectric constant for use as a copper diffusion barrier. Copper diffusion barrier films comprise one or more layers of silicon carbide. Covering a copper layer with a single thin NDC pre-layer significantly increases the maximum allowable Q-time for wafer probing. However, after the Q-time, a void forms between NDC layer and the NDC pre-layer. This work proposes a new two-step NDC process and the optimization of the thickness of the NDC pre-layer. The process has the advantages of providing a high stability for parametric test and a long allowable Q-time. These advantages are achieved by changing the thickness of the NDC pre-layer. This new approach has been analyzed using TEM and by performing parametric tests, and the feasibility has been confirmed experimentally. No void is formed between the NDC layers and a high test stability is achieved when the thickness of the NDC pre-layer is 120 A.