Accurate and Efficient Interdependent Timing Model for Flip-Flop in Wide Voltage Region

Abstract

The interdependency of the setup and hold constraints and clock-to-q (c2q) delay for flip-flops (FF) has been studied in static timing analysis (STA) to facilitate timing closure and improve circuit performance. However circuits operating in near-threshold voltage (NTV) region pose severe challenge to the interdependent timing modelling due to its significant nonlinear relation and much wider constraint range compared with super-threshold voltage (STV) region. In this paper an accurate and efficient modelling approach is proposed by employing artificial neuron network (ANN) to characterize the interdependency among the setup time hold time and c2q delay of FF in wide voltage region. Experimental results show the prediction errors of c2q delay with varied setup and hold constraints are lower than 2.1% and 1.8% in NTV and STV regions with 3.51x and 1.09x accuracy improvement compared with the prior work. Besides the modelling efficiency is validated by 1.41 x/1.10x simulation cost reduction and 21.08x/4.14x library storage saving for NTV/STV domain with accuracy advantage.