Abstract
Operating in the Near Threshold Voltage (NTV) region improves the energy-efficiency of CMOS circuits by an order of magnitude. However, the number of hold-time violations significantly grows by scaling the supply voltage to the NTV region due to the increased delay variations. Furthermore, the conventional hold-time fixing approaches based on corner analysis are not applicable to the NTV region. In this paper, we propose a new iterative hold-time fixing flow for the NTV region based on Statistical Static Timing Analysis. The experimental results show 43.3% (35.4%) less energy (area) overhead compared to the conventional approach.
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