AccelSDP: A Reconfigurable Accelerator for Software Data Plane Based on FPGA SmartNIC

Xiaoying Huang,Mangu Song,Yunfei Guo,Zhichuan Guo

doi:10.3390/electronics10161927

Xiaoying Huang, Mangu Song + Show 2 more

Open Access

https://doi.org/10.3390/electronics10161927

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Abstract

Software-defined networking (SDN) has attracted much attention since it was proposed. The architecture of the SDN data plane is also evolving. To support the flexibility of the data plane, the software implementation approach is adopted. The software data plane of SDN is commonly implemented on a commercial off-the-shelf (COTS) server, executing an entire processing logic on a commodity CPU. With sharp increases in network capacity, CPU-based packet processing is overwhelmed. However, completely implementing the data plane on hardware weakens the flexibility. Therefore, hybrid implementation where a hardware device is adopted as the accelerator is proposed to balance the performance and flexibility. We propose an FPGA SmartNIC-based reconfigurable accelerator to offload some of the operation-intensive packet processing functions from the software data plane to reconfigurable hardware, thus improving the overall data plane performance while retaining flexibility. The accelerated software data plane has a powerful line-rate packet processing capability and flexible programmability at 100 Gbps and higher throughput. We offloaded a cached-rule table to the proposed accelerator and tested its performance with 100 GbE traffic. Compared with the software implementation, the evaluation result shows that the throughput can achieve a 600% improvement when processing small packets and a 100% increase in large packet processing, and the latency can be reduced by about 20× and 100×, respectively, when processing small packets and large packets.

Highlights

In recent years, software-defined networking (SDN) has attracted considerable attention and consists of application, control, and data planes
Our evaluation was performed under the assumption that the cached-rule table had already been generated, because assessing which caching policy is used to generate which kind of cached-rule table is beyond the scope of this paper
The evaluation is organized as follows: first, we evaluate the hardware implementation of the matching methods involved in the offloaded function units (OFUs) including longest prefix matching (LPM) and Exact Match (EM), some hardware-implemented actions, and the overall performance

Summary

Introduction

Software-defined networking (SDN) has attracted considerable attention and consists of application, control, and data planes. For better flexibility and more efficient communication with the control plane, many works have implemented a data plane based on software [1,2,3,4,5], with a commodity CPU bearing the burden of the intensive packet processing. These software implementations have made full use of user space I/O libraries (i.e., Intel DPDK), non-uniform memory access (NUMA) architecture, and some other emerging techniques linked to the current network interface card (NIC) Application Specific Integrated Circuits (ASICs) to improve processing efficiency. With the flexibility and performance brought by the FPGA and the tractability from the NIC ASIC, an FSNIC is surely the most suitable hardware to implement our reconfigurable accelerator

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