Profiling and SW/HW co-design for efficient SDN/openflow data plane realization

Abstract

Software defined networking (SDN) is used to provide as a centralized control with a flexible and scalable network. Also, SDN is provisioned for the communication systems of the next generation. OpenFlow is treated as a leading standard that defines the interface between the control plane and the physical network (data plane). Formaintaining the flexibility for the various network applications, software switches are mainly chosen to be implemented in commodity servers. However, the software-based solution will suffer from low performance especially when the network topology is getting larger and more complex. In this paper, we build an analytical model and deliver aperformance profiling against an OpenFlow software switch, Open vSwitch (OvS). OvS is the most widely used software switch for the SDN's data plane thereby being suitable for the analysis in research. Furthermore, a software and hardware (SW/HW) co-designed structure is proposed to accelerate the specific functions that are involved in the packet processing in the software switches. Based on this structure, a network administrator can advance on accelerating the data plane in a more flexible and programmable System-on-Chip(SoC) design. To validate the consequence, the proposed SW/HW co-designed scheme is implemented on a Xilinx Zynq SoC platform. Theimplemented result shows that a receiving packet processing in a matching flow can reduce up to 36.26% and 74.36% of the latency for the short packet header in two extreme cases and 80.86% and 75.92% of the latency for the long packet header compared with the latency bya software-only switch.