Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction

Abstract

Different fault injection techniques based on simulation have been proposed in the past for functional verification of register transfer level (RTL) IP models. They allow designers to model any type of fault and provide the quality of test patterns through the fault coverage estimation. Nevertheless, the low speed of such a cycle-accurate RTL simulation involves a trade-off between the simulation time and the achieved fault coverage. On the other hand, Transaction-level modeling (TLM) allows a simulation speed-up up to 1000x with respect to RTL. This paper presents a methodology to accelerate RTL fault simulation through automatic RTL-to-TLM abstraction. The methodology abstracts injected RTL models into equivalent injected TLM models thus allowing a very fast automatic test pattern generation at TLM level. The paper shows how the generated TLM test patterns can be automatically synthesized into RTL test patterns by exploiting the structural information of the RTL model extracted during the abstraction process. Experimental results have been applied to several designs of different size and complexity to show the methodology effectiveness.