Accelerated techniques in stem fault simulation

Abstract

In order to cope with the most expensive stem fault simulation in fault simulation field, several accelerated techniques are presented in this paper. These techniques include static analysis on circuit structure in preprocessing stage and dynamic calculations in fault simulation stage. With these techniques, the area for stem fault simulation and number of the stems requiring explicit fault simulation are greatly reduced, so that the entire fault simulation time is substantially decreased. Experimental results given in this paper show that the fault simulation algorithm using these techniques is of very high efficiency for both small and large numbers of test patterns. Especially with the increase of circuit gates, its effectiveness improves obviously.