Accelerated Shift Registers for X-tolerant Test Data Compaction

Abstract

In this paper we present a method for compacting test response data without the need for additional X-masking logic by using the timing flexibility of modern automatic test equipment (ATE). In our design the test response is compacted by several multiple input shift registers without feedback (NF-MISR). The shift registers are driven by a clock which is k times faster than the slower test clock of the scan chains. For each test clock cycle only one out of the k different outputs of each shift register is evaluated by the ATE. To mitigate the negative effects of consecutive X values within the scan chains, a permutation of the NF-MISR inputs is periodically applied. Thus, no additional external control signals or test set dependent control logic is required. The possibilities of an implementation on a Verigy ATE will be described. The presented results for three industrial circuits demonstrate the effectiveness of the proposed approach in comparison to a commercial ATPG tool.