Abstract
Machine Vision (MV) has become an increasingly popular technology in Industry 4.0 for advanced manufacturing processes. Specially, assembly lines require fast MV of the machine objects, assembly-functions, and operations to improve accuracy and quality. In order to achieve this, MV deployed customized Application Specific Integrated Circuits (ASICs). These ASICs designed to run Convolution Neural Network (CNNs) and perform AI inference. The processing needs high performance computing (HPC) of a large number of tensors with least energy spending in the ASICs. In the paper, we propose a design approach for efficient tensor processing in tensor cores for accelerated AI inference at CNN based MV in ASICs. The design approach deploys the small DNN (Deep Learning Neural Network) model SqueezeNext along with application of quantization, fast arithmetic reduction, tensor cores aware tuning, pruning, and fusion for the efficient AI inference in ASICs. Successful implementation of proposed design can provide a competitive advantage to industries in terms of quality and cost of product along with time saving in manufacturing process.
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