Abstract
We report a simulation-based study of an all-silicon novel device which exploits internally combined quantum mechanical band-to-band and barrier tunneling mechanisms to overcome the intrinsic low current drive limitations of conventional silicon Tunnel FETs and the 60mV/decade limitation of MOSFETs at room temperature. The new switch is a gated m–i–n+ structure which has an ultra-thin dielectric between metal source and silicon channel. Numerical simulations predict sub-60mV/dec average subthreshold slope (SS ∼43mV/dec) and a uniquely high ION/IOFF ratio (∼1011). The device principle and the potential performances are investigated by numerical simulation. We evaluate the impact of the tunneling layer thickness on device performances and compare single and double gate architectures. Finally, we assess the impact of device gate length scaling on its performances, which is different from Tunnel FET: we observe an improvement of SS and ION values at smaller gate lengths.
Published Version
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