About the features of the verification of VLSI class “System on a chip” for complex information systems

Abstract

The article discusses the hierarchical levels of the verification process for VLSI of the System-on-Chipclass, as well as information systems built on their basis. The increasing complexity of modern information systems creates additional requirements for the composition and complexity of the verification of such systems, including the early stages of their development. An approach to verification is proposed using a combination of software tools for modeling digital circuits at the lower levels of abstraction and specialized verification tools developed for a specific information system and implementing verification primarily at the system level. The proposed approach will enhance the performance of VLSI modeling of the System-on-Chip class, which will improve the reliability of verification of complex systems by improving test coverage. It is noted that when connecting mutually asynchronous fragments of VLSI it is necessary to carry out modeling at a high level, able to identify problems of data transmission between individual synchronous subsystems.