A yield-centric perspective on the growing eBeam role in patterning control

Abstract

Listen

Translate article

As semiconductor end markets diversified from computers and Internet to mobile and social media, computing demand increased from hundreds of millions to billions of units. With the advent of AI, and big data end markets further diversified to IOT, communications, self-driving cars, power, and sensors, resulting in demand for computing that ski-rocketed to the trillions. To fuel this growth PPACt :Power, Performance, Area-cost and time-to-market needed to accelerate. This acceleration is enabled by new architectures, 3D structures, new materials, new ways to shrink, and advanced packaging. An obstacle limiting this growth was identified as loss of correlation between the new aforementioned semiconductor device structures, and the measurements conventional optical workhorse metrology provided. This was not a one-time calibration event. Optical metrology increased reliance on accuracy check, ground truth and calibration is a result of increasing optical metrology accuracy gaps over time, causing inflating edge placement error budgets, instability in litho to etch bias and non-zero offset over time. A paradigm shift in overlay, CDU, and edge placement error patterning control metrology was sought to accelerate PPACt at needed yield. This talk tells the story of how to introduce a new standard to a needing industry. We start with addressing the need for a new technology enabling a fast non-destructive accurate inline metrology, we then validate its accuracy overtime using two different industry standard reference metrologies. And we conclude with testimonies of chipmakers showcasing the use of the new industry standard of patterning control. To enable high throughput accuracy in overlay, EPE, and NZO metrology a highly efficient BSE see-through ebeam technology was introduced and benchmarked against optical metrology. Showing reduced non zero offset residuals on device, with the capability to accurately gauge litho-to-etch bias. As a good engineering practice STEM and Delayer techniques validated the accuracy of the inline ebeam technology so it could become the new workhorse to assume the role of HVM overlay metrology. We conclude with three chipmakers case studies of how the use of the new workhorse ebeam metrology accelerated cycles of development, reduced reliance on destructive metrology enabling faster process splits in fabrication of three dimensional nanosheet transistors, faster ramp of semiconductor manufacturing and better yield by better on device overlay and NZO at HVM.