Imaging-based overlay metrology optimized by HV-SEM in 3D-NAND process

Abstract

Optical overlay metrology has been adopted for years as baseline for overlay control in semiconductor manufacturing. More stringent overlay budget for securing good product yield has been required as device dimension shrinkage. For effective and tight overlay control, the traditional optical overlay metrology has faced two primary challenges of increasing the measurement accuracy and minimizing the measurement variance between overlay mark in scribe lane and in-die device pattern. Overlay mark asymmetry is one of the general factors to induce optical overlay metrology error. While 3D-NAND deep-etch processes would induce within-wafer mark asymmetry which worsens measurement robustness of optical overlay metrology. Accurately determining on-product overlay (OPO) errors at both after-develop inspection (ADI) and after-etch inspection (AEI) is also desirable in 3D-NAND process for applying non-zero offset (NZO) at photo exposure. To address the measurement robustness of optical overlay metrology in 3D-NAND process, also for accurately bridging the scribe lane based optical overlay metrology to OPO metrology, a complementary overlay metrology by high voltage scanning electron microscope (HV-SEM) was adopted as the reference metrology for optimizing the optical measurement condition on scribe lane targets. In this paper, the measurement accuracy of imaging-based overlay (IBO) target under various optical conditions was calibrated by HV-SEM. HV-SEM can measure both the scribe-lane and in-device targets via capturing buried structures, and it was employed to bridge the measurement results from IBO and in-device target. Then the optimal optical metrology can be decided for both ADI and AEI to facilitate effective advance process control (APC) and NZO purpose.