A word-level graph manipulation package

Abstract

Verification has become one of the most important steps in circuit design. In this context, the verification of circuits described at the register-transfer level by means of hardware description languages (HDLs), like VHDL, becomes increasingly important. Decision diagrams (DDs) have proved successful for the representation of HDL expressions, like data-path operations or control logic. Unfortunately, there exists no graph type that can represent both word-level (i.e., data-path) and bit-level (control logic) functions with the same efficiency. Consequently, it is important to support multiple graph types in a graph manipulation package. This paper presents a word-level graph manipulation package [18] that provides a variety of different DDs and – even more important – enables operations between them. Furthermore, a complete set of data-path operations is given that can formally be verified based on word-level decision diagrams (WLDDs). The presented techniques allow a direct translation of HDL expressions to WLDDs. New algorithms for modulo and division on WLDDs are presented which turn out to be the core of the efficient verification procedures. The efficiency of the package is demonstrated by a large number of experiments. Finally, in a case study it is shown how the different package features interact and outperform conventional approaches.