Abstract
This article explores a design space for bandwidth enhancement of two-stage Doherty power amplifier for higher back-off based on same devices. This design space analysis shows that for any back-off level, a number of bandwidth enhancement solutions can be obtained with various combinations of design parameters for load combiner and load impedance. Therefore, the proposed scheme explores design space in terms of optimum design parameters for load combiner and load impedance for best bandwidth and realizability at a high back-off. The proposed design methodology is validated with a two-stage Doherty power amplifier using 25 W packaged Gallium Nitride High Electron Mobility Transistors. This Doherty power amplifier provides measured drain efficiency between 66% to 73.8% at saturation and 45% to 63.6% at 8-9 dB output power back-off from 1.7 to 2.025 GHz. Measurement with WCDMA signals shows that the adjacent channel power ratio is better than −46 dBc after applying digital predistortion.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: International Journal of RF and Microwave Computer-Aided Engineering
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
