A wideband power amplifier with 13.2 dBm Psat and 19.5% PAE for 60∼94 GHz wireless communication systems in 90 nm CMOS

Abstract

A wideband power amplifier (PA) for 60∼94 GHz transceivers using standard 90 nm CMOS technology is reported. The PA comprises a two-stage common-source (CS) cascaded input stage with wideband T-type input, inter-stage and output matching networks, followed by a two-way CS gain stage using Y-shaped power divider and combiner, and a four-way CS output stage using dual Y-shaped power divider and combiner. Instead of the traditional area-consumed power divider and combiner with all ports impedance matching to 50 fi, in this work, Y-shaped and dual Y-shaped power divider and combiner that constitute miniature low-loss transmission-line inductors are used for more flexible inter-stage impedance matching and easier bias design. The PA consumes 90 mW and achieves power gain (S21) of 16 dB, 21 dB and 10.4 dB, respectively, at 60 GHz, 77 GHz and 94 GHz. In addition, the PA achieves excellent saturated output power (PSAT) of 13.2 dBm, 12 dBm and 10.6 dBm, respectively, at 60 GHz, 77 GHz and 94 GHz. The corresponding maximal PAE is 19.5%, 16% and 8.9%, respectively, at 60 GHz, 77 GHz and 94 GHz. These results demonstrate the proposed PA architecture is promising for 60∼94 GHz communication systems.