Abstract

A fractional-N frequency synthesizer with a fractional bandwidth of 67% for UHF/VHF-band mobile broadcasting tuners is presented. A novel linearized coarse tuned VCO with a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth. The proposed technique successfully reduces the variation of K <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VCO</sub> and per-code frequency step by 2.7 and 2.1 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) structure is employed for high speed operation, low power consumption, and small silicon area. Implemented in 0.18-mum CMOS, the PLL covers 154 ~ 303 MHz (VHF) and 462 ~ 911 MHz (UHF) with a single VCO. The integrated phase noise is 0.807 and 0.910 degree for the integer-N and fractional-N modes, respectively, at 827.5-MHz output frequency. The in-band noise at 1 kHz offset is -95 dBc/Hz in the integer-N mode and degraded only by 3.8 dB in the fractional-N mode.

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