Abstract
Advanced high-speed systems such as DDR3, GDDR5, XDR use double-data-rate (DDR) signaling to increase memory bandwidth where data bits are sent on both positive and negative edges of the clock. To achieve the same timing margins on both edges, a duty cycle corrector (DCC) is used to achieve 50% duty cycle. This paper proposes a programmable mixed-signal DCC. The DCC is implemented in TSMC 65 nm technology. Experiment results show that proposed DCC works up to 7 GHz operating frequency for 30% - 70% input duty cycle range and produces output duty cycle with an error below ±1%.
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