A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs

Abstract

SUMMARY A wide-range multiphase delay-locked loop (DLL) us-ing mixed-mode voltage-controlled delay lines (VCDLs) is presented. Anedge-triggered duty cycle corrector is introduced to generate output clockswith 50% duty cycle. This DLL using an analog 3-states phase-frequencydetector (PFD) and the proposed digital PFD can achieve low jitter oper-ation over a wide frequency range without harmonic locking problems. Ithas been fabricated in a standard 0.25-µm CMOS technology and occu-pies a core area of 1mm 2 including the on-chip regulator and loop filter.For reference clocks from 20MHz to 550MHz, all the measured rms andpeak-to-peak jitters are below 10ps and 78ps, respectively. key words: DLL, clock generation, wide range, duty cycle correction 1. Introduction Delay-locked loops (DLLs) have been widely used in clockde-skew buffers, multiphase clock generators [1], edge-combined frequency synthesizers [2],[3] and the clocksources for serializer/deserializer interfaces [4]. A wide-range multiphase DLL will enlarge the operating range andprovide the flexibility for digital systems. ConventionalDLLs can only operate over a small range because the rangeof the voltage-controlled delay line (VCDL) is limited [5].If the ratio of maximum to minimum reference clocks fora DLL is more than ten, a large gain,