A VLSI implementation of residue adders

Abstract

The efficient hardware implementation of residue number system (RNS) architectures has evolved based on the development of integrated circuit technology. The implementation of RNS adders is discussed in this paper. Three approaches (the binary adder, the look-up table, and the hybrid implementation) are analyzed in the scope of VLSI criteria where the performance measures are area and time. Two layout design procedures have been used. They are flexible and support any type of moduli. The implementation complexity depends on the form and size of the modulus, but, in general, the look-up table approach is preferable in both area and time for moduli up to five bits, while the binary adder and the hybrid approaches offer better performance for larger moduli.