Abstract
This paper presents a design of VLSI architecture for the FEC (Forward Error Correction) decoding system supporting the Chinese National Terrestrial Digital TV Broadcasting Standard (GB20600-2006). The architecture of the FEC decoder includes a time-deinterleaver; a Symhol-to-Bit LLR calculator, a LDPC decoder, a BCH decoder, and a de-randomizer. The FEC decoder supports 5 modulation modes (64QAM, 32QAM, 16QAM, 4QAM and 4QAM-NR), 3 rates of LDPC codes (0.4, 06, and 0.8) and 3 kinds of time-interleaver lengths. The implementation has heen both prototyped in a FPGA board and silicon-proved by a single-chip DTMB demodulator and FEC ASIC chip. For 64 qam, rate 0.6 modes, the FEC decoder can achieve the threshold of visibility (TOV) at 14.2 dB.
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