A very low power and high throughput AES processor

Abstract

In this paper we presents the design of a very low power and high throughput AES processor. A sophisticated AES algorithm without sacrificing its security features, throughput and area is used to design the processor. Due to the optimization of the algorithm and a number of design considerations, the processor shows its superiority over other AES processors. The proposed processor is simulated on the FPGA platform and Quartus II development software of Altera device of family Stratix II GX is used to simulate the design. A Power Play Early Power Estimation Tool is used to approximate the power consumption of the proposed processor. Later on the more reliable power analysis tool named Power Play Power Analyzer is used to estimate the static and dynamic power dissipation in the Processor. The high level of system integration along with very low power consumption and high throughput makes the AES processor an ideal choice for a range of application including small computing devices, smart card readers and network applications like WLAN, WPAN, WSN etc.