A Vertical Superjunction MOSFET With n-Si and p-3C-SiC Pillars

Abstract

A vertical superjunction (SJ) MOSFET with n-Si and p-3C-SiC pillars is introduced. Since 3C-SiC has $4\times $ higher breakdown electric field than Si, the sensitivity of the breakdown voltage ( ${V}_{\text {B}}$ ) to charge imbalances is weakened, which helps to improve the tradeoff between the specific ON -resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ ) and ${V}_{\text {B}}$ . In addition, since the n-Si/p-3C-SiC junction stays off at the ON -state of the body diode and the hole mobility in 3C-SiC is low, the reverse recovery charge ( ${Q}_{\text {rr}}$ ) is reduced and the resistance of the p-pillar is increased, which suppresses electric oscillations during reverse recovery. With the optimum design, the proposed SJ MOSFET obtains a 2%–11% lower ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ than the conventional SJ MOSFET. Numerical simulation results of 600-V designs show that the proposed SJ MOSFET has a 7% lower ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ , a 39% lower ${Q}_{\text {rr}}$ , and much smaller electric oscillations during reverse recovery compared to the conventional SJ MOSFET.