A Variation Aware Register Clustering Methodology in Near-Threshold Region

Abstract

Near threshold voltage (NTV) design has gained significant attention due to its optimal energy efficiency. However, circuits are highly sensitive to process variations at NTV, which poses great challenges for clock network design. In this paper, we propose a variation aware register clustering methodology for clock network design at NTV. The timing-driven and load-balanced methods are implemented to reduce clock skew and sensitivity to process variation of clock skew at NTV. Experiment results show that our algorithms reduce the skew by 37.7% and skew variation (σ) by 16.4% with only 3.2% increase on power consumption.